CrossConnect for ARM Release Notes
- Improved ADIv5 memory access.
- Added support for v7A and v7EM architectures.
- Added support for Feroceon devices.
- Improved performance for AVR version of CrossStudio.
- Added dynamic loading support for AVR version of CrossStudio.
- Increase maximum scan chain length.
- Fixed lock up in ADIv5 word and half word accesses when using unaligned start addresses.
- Fix corrupted flag bits when debugging in THUMB mode on ARM9 devices.
- Improved setting of TCK frequency.
- Improved ARM9 performance.
- Improved JTAG daisychaining performance.
- Added the ability to enable and disable "fast" ARM7/ARM9 memory accesses.
- Add workaround for problem accessing FIO registers on LPC2000 devices.
- Add ADIv5 JTAG IR/DR PRE/POST clocking.
- Add arbitrary JTAG IR & DR clocking.
- Fix debugging THUMB mode on synthesized ARM9 devices.
- ADd support for dynamically modifying the JTAG parameters.
- Now supports ADIv5 (Cortex-M3).
- Support 7-bit XScale IR.
- Fix XScale JTAG IR/DR PRE/POST clocking.
- Improved adaptive clocking support.